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Make and Makefile

10 August, 2020   ·   Tools
  https://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/   https://www.gnu.org/software/make/manual/make.html   https://www.gnu.org/software/make/

make is a tool responsible for generating binary and other non-source files of a program from the program’s source.

make can be used to compile source code of any language.

Features

A Makefile contains instructions for make to run. A series of instructions are known as a rule. A Makefile also describes relationship among files.Example of a simple rule:

target … : prerequisites …
        recipe
        …
        …

make uses tab for indentation. Failing to use it would throw an error

Makefile Processing

Variables

objects = main.o kbd.o

edit : $(objects)
        cc -o edit $(objects)
main.o : main.c defs.h
        cc -c main.c
kbd.o : kbd.c defs.h command.h
        cc -c kbd.c
clean :
        rm edit $(objects)

Implicit Rules

make has an implicit rule for updating .o file from a correspondingly named .c file using cc -c command.

when a .c file is used through implicit rule, it is also added to the list of prerequisites. Hence, .c files can be omitted from prerequisites’ list.

Example:

objects = main.o kbd.o command.o display.o

edit : $(objects)
        cc -o edit $(objects)

main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h

.PHONY : clean
clean :
        rm edit $(objects)

when using implicit rules, an alternate way of writing Makefile can be used. in this type of Makefile, entries are grouped by their prerequisites instead of by their targets

Example:

objects = main.o kbd.o command.o display.o

edit : $(objects)
        cc -o edit $(objects)

$(objects) : defs.h
kbd.o command.o files.o : command.h
display.o : buffer.h

Cleaning Directory

make can clean a given directory. for that Makefile should have an explicit .PHONY target.

.PHONY prevents make to confuse it with an actual file target and causes it to continue in spite of errors from rm.

taget clean can be executed by passing it as an arg to make

clean should not be placed at top of the Makefile. Otherwise it would become global target and will be executed by default.

.PHONY : clean
clean :
        -rm edit $(objects)

what a Makefile may contain

  1. variable definitions
  2. directives (instruction for make to do something special while reading the makefile)
    • Reading another makefile
    • deciding whether to ignore a part of Makefile
  3. comments (starts with #). for multiline comment, a backslash should be used at breakpoints

Including other Makefile

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